This is the project homepage for wb_spimaster, an SPI master engine for the Wishbone bus, written in VHDL.
The wb_spimaster module is a configurable SPI master engine which can be controlled from the Wishbone bus interface. It allows the user to configure several SPI parameters.
The SPI master engine is made up of a shift engine component which controls the SPI bus. The Wishbone interface is provided by a front-end entity to that shift engine.
Using the wb_spimaster component in your VHDL design is as easy as declaring and instantiating any other component. Below is the VHDL entity declaration of the component.
entity wb_spimaster is generic ( dat_sz : natural := 8; slv_bits: natural := 3 ); port ( clk_i : in std_logic; rst_i : in std_logic; -- -- Whishbone Interface -- adr_i : in std_logic_vector(1 downto 0); dat_i : in std_logic_vector((dat_sz - 1) downto 0); dat_o : out std_logic_vector((dat_sz - 1) downto 0); cyc_i : in std_logic; lock_i : in std_logic; sel_i : in std_logic; we_i : in std_logic; ack_o : out std_logic; err_o : out std_logic; rty_o : out std_logic; stall_o: out std_logic; stb_i : in std_logic; -- -- SPI Master Signals -- spi_mosi_o : out std_logic; spi_miso_i : in std_logic; spi_nsel_o : out std_logic_vector(((2 ** slv_bits) - 1) downto 0); spi_sclk_o : out std_logic ); end wb_spimaster;
The design is customizable through a few generics, which are described in the following table.
|Width of Wishbone data bus. This also determines the size of the engine’s registers. The module will probably not work if this generic is set to a value < 8.|
|Determines how many SPI slaves are supported by the module. The module will support (2 ^ slv_bits) SPI slaves. Example: If the generic is set to 3, the module will support up to eight SPI slaves. The module cannot support more slaves than the value of the dat_sz generic.|
The module supports Wishbone classic read and write cycles. It will generate a response within one clock cycle. The response output, i.e. ack or err is asserted as long as the module’s stb input is active. Because the module generates a response within one cycle, it does never drive the stall output. Nevertheless, it should support Wishbone classic pipelined read and write cycles, too, but that hasn’t been tested so far.
The module exposes four registers which are described in the table below.
|Rx/Tx Data||Data written to this register will be transferred out of the SPI engine during the next transfer. Data shifted into the SPI engine during the last transfer can be read from this register.|
|Control||SPI engine control registers. The meanings of the bits are described in the table below.|
|nSEL||Value of the engine’s SPI nSEL output pins.|
|Divider||SPI clock divider. The SPI clock is derived from the logic clock and divided by this factor, i.e. setting this register to a value of 8 will cause the SPI clock to run at 1/8 of the logic clock frequency.|
The module’s control register allows the user to adjust SPI parameters and control the transfer.
|0..2||Count||Determines how many bits will be shifted on the next SPI transfer.|
|4||CPOL||Controls the SPI clock polarity (CPOL).|
|5||CPHA||Controls the SPI clock phase (CPHA).|
|7||Start/Busy||Setting this bit starts an SPI transfer. While the SPI transfer is in progress, this bit will read back active. Once the SPI transfer has completed, the bit is cleared. Attempts to set this bit while already set, i.e. an SPI transfer is in progress, will cause an err response on the Wishbone bus.|
Below are the links to the VHDL file(s).
Here are a few links related to this project.